1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which comprises one or more memory cell arrays erasable collectively in response to a command input from the outside, each memory cell array having a plurality of a sidewall type memory cell arranged in a matrix form of rows and columns and each sidewall type memory cell comprising a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and a memory functional element formed on either both or one side of the gate electrode and having the function of retaining charges. More particularly, the present invention relates to a method of erasing the data in a nonvolatile semiconductor memory device.
2. Description of the Related Art
A common erasable programmable read only memory (EPROM) incorporates a memory cell of a metal-oxide-semiconductor (MOS) structure with an electrically insulated floating gate. The data of interest is stored in the memory cell according to the amount of charges at the floating gate. A flash memory is one type of the EPROMs. The flash memory typically has a memory cell array structure similar to the EPROM. The memory cell array is consisted of word and column. Each memory cell is located at the intersection between a word line and a bit line. The word line is connected to the control gates of memory cells arranged along each row while the bit line is connected to the drains of memory cells arranged along each column. All the memory cells are connected at the source to a common source line. The flash memory can be programmed by a user. Once the flash memory has been programmed, it holds a programmed data before an erasing action is called. When the flash memory is applied at its source with an erasing voltage, the data throughout its memory cell array can be erased. After the erasing action, the flash memory remains programmable with a new data.
Such a conventional flash memory is however unfavorable in the erasing property of the memory cell array. When a program code or data stored in the memory cell array is modified partially or entirely, it has to be completely rewritten by a modified version of the program code or data with the memory cell array cleared off thoroughly.
For eliminating such a drawback, the conventional flash memory is modified to employ a method of dividing the memory cell array into blocks and erasing desired one of the blocks through applying an erasing voltage to the source of the memory cells in the block. The block erasing method allows one target block in the memory cell array but not all the memory cell array to be erased selectively. For example, a nonvolatile semiconductor memory device employing the method is disclosed in Japanese Patent Laid-open Publication NO. 6-215587.
As flash memories gain a large share in the market of nonvolatile semiconductor memory devices, flash memory compatible types of nonvolatile semiconductor memory devices are now introduced. One of them is a sidewall type. The sidewall type of nonvolatile semiconductor memory devices is a multi-bit memory capable of storing two bits in each memory cell and its memory cell size is smaller than that of flash memories, thus being favorable in the higher integration. Also, as the sidewall type is based on a logic process (a manufacturing process for logic circuits), its manufacturing cost is relatively lower than that of flash memories. A sidewall type memory cell used in the sidewall type of nonvolatile semiconductor memory devices will now be explained in more detail, referring to FIG. 3.
The sidewall type memory cell has a gate electrode 217 provided via a gate insulating layer 214 on a P-type semiconductor substrate 211 thereof A pair of N-type diffused regions 212 and 213 acting as source or drain areas are developed on both sides of the gate electrode 217 on the P-type semiconductor substrate 211. The diffused regions 212 and 213 are arranged in an offset form. More specifically, the diffused regions 212 and 213 extend short of beneath the gate electrode 217 while each offset region 271 beneath a charge holding layer forms a part of the channel region. A silicon nitride layer 242 is provided as the charge holding layer for holding charges at the trap level on each side of the gate electrode 217 and sandwiched between two silicon oxide layers 241 and 243 thus forming an ONO structure of the sidewall. The silicon nitride layer 242 functions as a memory functional element for holding charges. The memory functional element refers to a part in which charges are actually accumulated by rewriting operation in the memory functional element or the charge retaining film.
The charge holding regions (the silicon nitride layer 242) in each of the memory sections 261 and 262 are overlapped with the diffused regions 212 and 213 respectively. The overlapping allows at least portions of the charge holding layer (the silicon nitride layer 242) to extend above at least the portions of the diffused regions 212 and 213.
The above described structure is featured not to permit over erasing. The over erasing means to lower the threshold voltage from its lower limit to be controlled. For example, a NOR flash memory may have the threshold voltage declined to not higher than 0 V by the over erasing. When the threshold voltage has been declined to lower than 0 V, a potential difference between the source and the drain will cause a flow of current with no application of a positive voltage at the control gate in the NOR flash memory. It is hence hardly distinguished between the readout action of measuring the current across a target or selected memory cell of which the control gate is supplied with a positive voltage and the readout action of measuring the current across an unselected memory cell where the over erasing is done. As a result, the data to be output will be lowered in the reliability.
The controlling of the threshold voltage will now be explained. A data stored in a flash memory is expressed by the amount of charges (electrons) received by the floating gate. More particularly, when the floating gate retains a greater number of electrons, the channel region will hardly develop an inversion layer, thus increasing the threshold voltage at the memory cell. On the other hand, when the floating gate releases electrons, the channel region will be allowed to develop an inversion layer thus decreasing the threshold voltage at the memory cell. In short, the state of the channel region in a flash memory directly depends on the number of retained electrons. However, in the sidewall memory described above, the gate electrode 217 is provided via the gate insulating layer 214 on the P-type semiconductor substrate 211, of which the structure is identical to that of an N-type MOSFET. Accordingly, the threshold voltage for the N-type MOSFET is at least compensated even when the memory section in the sidewall memory is overloaded with electrons and will never be declined to not higher than 0 V. This is the reason why the sidewall memory involves no over erasing and hence needs not to carry out a sequence of troublesome erasing actions including pre-conditioning process and post-conditioning process which are mandatory in a NOR flash memory for inhibiting the over erasing. The pre-conditional process is a programming action prior to the erasing process at a target memory cell for eliminating variations in the threshold voltage, whereby the target memory cell of which the threshold voltage is low can be protected from being over erased. The post-conditioning process is a moderate programming action of increasing the threshold voltage at a target memory cell which tends to become lower in the threshold voltage than the other memory cells after the erasing action.
It is desired that any nonvolatile semiconductor memory device of the sidewall type arranged compatible with a flash memory matches the specifications of the flash memory. This allows the sidewall memory to replace a flash memory without modifying the primary design of a system where the flash memory was installed. For example, the function of erasing data in each block is systematically contained in every known flash memory and will thus preferably be supported by the sidewall memory. Also, as the sidewall memory is designed to replace a flash memory, its performance should be advantageous over the flash memory, i.e., the erasing action is conducted at a higher speed.
However, the sidewall type memory cell is arranged to depend on which of the memory sections 261 and 262 is to be programmed, erased, or read with an electric field applied in one direction across the channel region. Therefore, the assignment of the diffused regions 212 and 213 is variable as the source and the drain respectively or vice versa. Accordingly, the sidewall memory unlike a flash memory needs not to connect the source of each memory cell with the common source line for erasing data on the block-by-block basis. Moreover, the block-by-block basis may be unfavorable in view of the energy saving.
In the sidewall memory, each memory cell is erased by a hot-hole implanting technique using the effect of inter-band tunneling. The inter-band tunneling is induced by a high-level reversed voltage applied to the PN junction between the substrate and the drain and a negative voltage applied to the gate for increasing the sharpness at the PN junction. More particularly, the erasing action of the sidewall type memory cell is substantially based on breakdown at the PN junction. Accordingly, the (erasing) current running from the memory cell for erasing data in the sidewall memory is greater than in the flash memory. More specifically, the current is substantially 100 nA per memory cell.
It is now assumed that the data is erased at once from each block which comprises 512 K (512×1024) memory cells. As each memory cell stores two bits, the storage capacity of the block is 1 M bits. When each of the 512 K memory cells draws 100 nA, the current of 50 mA is needed for erasing the block. It is hence required for collectively erasing data to increase the current supplying capacity of a voltage supplying circuit (namely, a charge pump circuit), the amplitude of voltage for offsetting a drop down in the voltage due to the current increase, or the size of a transistor which may be declined in the voltage during the erasing action. Those requirements will disadvantageously increase the current consumption and the overall chip area.
Also, with the fact that the charge pump circuit in a common flash memory delivers 1 mA of current at minimum, the total current of 50 mA for collective erasing will rarely be feasible. In other words, even when the sidewall memory is highly integrated to such a scale as of a flash memory, its action of erasing each block will hardly be implemented at the same performance as of the flash memory. It is hence needed an improved method of the sidewall memory erasing data at once in each block with highly integrated at the flash memory level. As the sidewall memory intends to replace a flash memory, its erasing action has to speed up as fast as the flash memory.